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A cryogenic CMOS chip for generating control signals for multiple qubits

Nature Electronics volume 4, pages 64–70 (2021)Cite this article

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Abstract

Scaled-up quantum computers will require control interfaces capable of the manipulation and readout of large numbers of qubits, which usually operate at millikelvin temperatures. Advanced complementary metal–oxide–semiconductor (CMOS) technology is an attractive platform for delivering such interfaces. However, this approach is generally discounted due to its high power dissipation, which can lead to the heating of fragile qubits. Here we report a CMOS-based platform that can provide multiple electrical signals for the control of qubits at 100 mK. We demonstrate a chip that is configured by digital input signals at room temperature and uses on-chip circuit cells that are based on switched capacitors to generate static and dynamic voltages for the parallel control of qubits. We use our CMOS chip to bias a quantum dot device and to switch the conductance of a quantum dot via voltage pulses generated on the chip. Based on measurements from six cells, we determine the average power dissipation for generating control pulses of 100 mV to be 18 nW per cell. We estimate that a scaled-up system containing a thousand cells could be cooled by a commercially available dilution refrigerator.

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Fig. 1: The quantum–classical interface of a quantum computer.
Fig. 2: Corner floor plan and operation of the CMOS control chip.
Fig. 3: Benchmarking the cryo-CMOS control with a QD chip.
Fig. 4: Power dissipated at 100 mK when interfacing with the QD device.

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Data availability

The datasets generated and/or analysed during the current study are available from the corresponding author upon reasonable request.

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Acknowledgements

This research was supported by Microsoft Corporation and the Australian Research Council Centre of Excellence for Engineered Quantum Systems (EQUS, CE170100009). We thank R. Rouse for help with the chip tape out and M. Cassidy, S. Waddy, C. Marcus and L. Kouwenhoven for discussions. We acknowledge the facilities as well as the scientific and technical assistance of the Research and Prototype Foundry, a Core Research Facility at the University of Sydney, and a part of the Australian National Fabrication Facility (ANFF).

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Author notes

  1. These authors contributed equally: S. J. Pauka, K. Das.

Authors and Affiliations

  1. ARC Centre of Excellence for Engineered Quantum Systems, School of Physics, The University of Sydney, Sydney, New South Wales, Australia

    S. J. Pauka, Y. Yang & D. J. Reilly

  2. Microsoft Quantum Sydney, The University of Sydney, Sydney, New South Wales, Australia

    S. J. Pauka, K. Das, R. Kalra, A. Moini, M. Trainer, A. Bousquet, C. Cantaloube, N. Dick & D. J. Reilly

  3. Birck Nanotechnology Center, Purdue University, West Lafayette, IN, USA

    G. C. Gardner & M. J. Manfra

  4. Microsoft Quantum Purdue, Purdue University, West Lafayette, IN, USA

    G. C. Gardner & M. J. Manfra

  5. Department of Physics and Astronomy, Purdue University, West Lafayette, IN, USA

    M. J. Manfra

  6. School of Materials Engineering and School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA

    M. J. Manfra

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Contributions

S.J.P., K.D., A.M. and D.J.R. conceived the presented idea. K.D., A.M., Y.Y. and C.C. designed the CMOS chip and packaging. K.D., A.M., M.T., A.B. and N.D. performed the characterization experiments on the CMOS chip. The GaAs heterostructure was grown by G.C.G. and M.J.M., and the QD device was fabricated by S.J.P. S.J.P., K.D. and R.K. performed the experiment interfacing the CMOS chip to the GaAs QD device. S.J.P., K.D. and D.J.R. wrote the manuscript with input from all the authors.

Corresponding author

Correspondence to D. J. Reilly.

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Extended data

Extended Data Fig. 1 Calibration procedure for gate leakage measurements.

a, Quantum dot device used to extract gate leakage. Gates used are highlighted in red, and the current path used for the measurement is shown by the green arrow. b, Sample calibration trace, taken by sweeping the voltage on the LW gate, while the charge lock switch GHOLD is closed. The extraction process for gate voltage is indicated by arrows. c, The measured current through the QPC when the charge locking switch is opened. d, The extracted gate voltage held on the gate for a period of 30 minutes.

Extended Data Fig. 2 Extracted charge leakage as VHOLD is varied, prior to removal of charge noise.

a-g, Traces from which charge leakage is extracted in Fig. 3c, as VHOLD is varied, and prior to removal of charge noise. The large steps in the extracted gate voltage are caused by low frequency charge noise in the donor layer.

Extended Data Fig. 3 Extracted charge leakage as VHOLD is varied, after removal of charge noise.

a-g, Traces from which charge leakage is extracted in Fig. 3c as VHOLD is varied, following the removal of charge noise. Each trace is fit with a line, from which the leakage rate is extracted.

Supplementary information

Supplementary Information

Supplementary Figs. 1–4 and detailed discussion on the design of various blocks of the CMOS circuit.

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Pauka, S.J., Das, K., Kalra, R. et al. A cryogenic CMOS chip for generating control signals for multiple qubits. Nat Electron 4, 64–70 (2021). https://doi.org/10.1038/s41928-020-00528-y

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